AMD turns ROCm docs into two books, with an optimization guide covering MFMA and WMMA

AMD has introduced the ROCm Handbooks, a series of book-style guides that gather its ROCm documentation into one learning path. Two volumes exist so far, a Programming Guide and an Optimization Guide, both free in HTML and PDF.

Two volumes, one learning path

According to AMD, ROCm documentation is normally organized by component, with each one, such as HIP, documenting itself next to its API reference. The handbooks take a different route. They pull pages from several components, add chapters written for the books, and order everything as a sequence meant to be read from start to finish, for offline study as well as online.

The handbooks ship together with ROCm. When a new ROCm version is released, matching handbook versions follow, so the text should line up with the installed software. The AMD ROCm Programming Guide has been available since November 2025. The AMD ROCm Optimization Guide is the second volume, published in October 2026.

The Programming Guide targets developers new to ROCm and HIP who already know C++. It has four parts: getting started, core HIP programming, performance optimization and the ROCm platform itself. Core HIP programming covers streams, cooperative groups, HIP graphs and several kinds of memory, and includes five tutorials: matrix multiplication, histograms, k-means clustering, stencils and a breadth-first search. The platform part covers installing ROCm, the Runfile Installer and building from source. AMD says its examples run on any AMD GPU that ROCm supports, from Radeon workstation cards to Instinct data center parts.

The Optimization Guide starts with profiling

The second volume is for experienced HIP programmers and AI developers working on low-level code. Its stated principle is to measure first and optimize second. Three worked patterns build on each other: a reduction, a histogram and a matrix multiplication. The last uses 4096 x 4096 single-precision matrices and runs through seven steps, from a naive baseline to LDS tiling, register tiling, double buffering, vectorized loads, tuning with __launch_bounds__ and a policy-based kernel template that dispatches by GPU architecture. For most steps, AMD says, the guide lists the profiler counters to watch so readers can check the effect on their own hardware.

A third part documents compiler builtins by architecture. It covers cross-architecture arithmetic and wavefront operations, MFMA matrix instructions for CDNA parts from the Instinct MI100 to the MI350 Series, and WMMA instructions for RDNA 3 and RDNA 4. Each matrix chapter plugs that architecture’s instructions into the generic matrix multiplication kernel from the patterns part.

Readers can open either volume online or download the PDF. The sources sit in two GitHub repositories, where AMD asks readers to file issues for mistakes or missing topics, and example code is in the ROCm examples repository.

Documentation as part of the CUDA rivalry

The release is documentation rather than silicon or software, but it speaks to AMD’s biggest practical gap against Nvidia: developers who already know how to write fast GPU code for CUDA need a clear route to doing the same on Instinct and Radeon. A guide that walks from a naive kernel to architecture-specific matrix instructions is aimed squarely at that switch, and at the AI engineers who tune kernels by hand.

Recent AMD engineering posts show where that tuning work is happening. AMD’s profiling of DeepSeek-V4-Flash training, which we covered on November 5, took step time from 556 ms to 239.8 ms. Its PrimusClaw agent runtime, reported on November 6, has logged 40,000 sessions on Instinct GPUs. Both depend on engineers who can read a profiler and reshape kernels, which is the skill the Optimization Guide’s profile-first approach is built to teach.

What the announcement leaves open

The post is a table of contents, not a performance claim, and AMD publishes no speedup figures for the optimization patterns. Whether the books are better than the existing component documentation is for readers to judge, and the source offers no reader numbers or feedback. It also does not say which ROCm version the current editions match, how often they will change, or whether more volumes are planned beyond the two. AMD says only that new handbook versions arrive with each ROCm release.

For now, the guidance in the post is simple. Newcomers should begin with the Programming Guide, working through the getting started section and the SAXPY tutorial. Those already writing HIP can go straight to the Optimization Guide. Developers tuning compute-bound kernels on Instinct or Radeon hardware can jump to the builtins chapter for their architecture.