AMD’s EPYC Embedded 9006 packs 256 cores and PCIe Gen 6 into test rigs and firewalls

AMD has introduced the EPYC Embedded 9006 Series SP7, its first embedded processors on the “Zen 6” architecture, with up to 256 cores and 512 threads. The 128-core model ships from Nov. 15; the other SKUs are due by year-end.

Up to 256 cores, 96 PCIe Gen 6 lanes

The 9006 family targets three embedded markets: semiconductor automated test equipment (ATE), network firewalls and enterprise storage. AMD says the chips deliver up to 1.8x the throughput of the 5th Gen EPYC 9005 generation. It also claims up to 1.5x the I/O bandwidth and up to 2.7x the memory bandwidth.

The memory system has sixteen DDR5 channels. They run RDIMMs at up to 8,000 MT/s and the newer MRDIMMs at up to 12,800 MT/s. On the I/O side, a socket offers up to 96 PCIe Gen 6 lanes at 64 GT/s, with CXL 3.1 for memory expansion, accelerators and storage.

Customers can pick from SKUs with 64 to 256 cores. AMD does not give prices, clock speeds or power ratings for individual models in this announcement.

Where the chips are meant to go

For ATE, AMD describes the CPU as the control engine that drives memory and storage tests, and that runs more tests in parallel. Samsung’s memory planning team said it intends to use the chips with its DDR5 RDIMM and MRDIMM, its PCIe Gen 6 PM1763 SSD and a CXL memory module in manufacturing test. IEI said a single socket’s 96 lanes could let one rig test many Gen 6 SSDs in parallel.

For firewalls aimed at 400G and 800G networks, AMD pitches the CPU as the control-plane engine and claims up to 1.3x higher firewall throughput than the previous generation. Lanner’s NCA-6145 network appliance is built on the chip. In storage, AMD cites up to 1.5x on the ISA-L benchmark, which times functions such as compression and RAID. Portwell plans test-and-measurement platforms around it.

Security is also part of the pitch. AMD lists a hardware root of trust that supports post-quantum cryptography for firmware signing, a Security Processor that handles the trusted execution environment and VM memory keys, and the open-source Caliptra block for device attestation. The company promises seven years of product longevity. That matters in embedded work, where a test platform or appliance can stay in service far longer than a typical server.

Salil Raje, who runs AMD’s Adaptive and Embedded Computing Group, said the chips are “extending AMD CPU leadership by bringing data center-class compute to embedded systems”.

Server silicon, trimmed for long product lives

The embedded line builds on the server generation AMD launched on Nov. 10. In that release, AMD lists the flagship server EPYC 9996 at 256 cores per socket and 600W, with systems shipping from major server vendors and Azure and Oracle Cloud instances listed as coming soon. The embedded part therefore reuses the same core design but adds the long support window and firmware cadence that equipment makers want. AMD’s own benchmark notes put the embedded 9756 at 128 cores, so the headline 256-core count is a top-end SKU, not the first one to ship.

AMD’s server CPUs already sit next to AI accelerators. AMD says EPYC is the host CPU for the Google Cloud TPU 8tx, which Google pitched as keeping data and model weights sealed while a chip is working. The embedded chips carry that role down to the machines that test and protect the hardware behind AI data centers.

The performance figures need caution. They are all AMD’s own estimates, mostly against the 5th Gen EPYC 9005 family, and AMD notes that results can change when products reach the market. The throughput headline rests on a SPECrate 2017 integer comparison, in which AMD pairs a dual-socket 6th Gen system with 512 cores and fast MRDIMMs against a 384-core 5th Gen system on slower DDR5-6400 memory. That compares platforms with different core counts and memory, not like for like. AMD also notes that SPEC will retire the SPECrate 2017 benchmark on Nov. 17, 2026.

The announcement names no competing embedded chips and gives no price. Customers, including Samsung, Lanner and Portwell, speak of plans or of designs under way, not of shipping products, and the source does not say when systems built on the chips will reach buyers. For now, the buyers are equipment makers designing next-generation testers, appliances and storage controllers, not end users.